1. Field of the Invention
The present invention relates generally to a video signal inverting circuit and is directed more particularly to a circuit for inverting the polarity of a video signal in which a signal provided by taking a negative film by a television camera has to be inverted in polarity so as to invert the black and white levels thereof to provide a normal video signal.
2. Description of the Prior Art
If image informations on nega-films are recorded in a VTR (video tape recorder), there is an advantage that without printing the negative film on a printing paper such image can be viewed at any time by using a television receiver.
Therefore, it is proposed to pick up the negative film by the television camera and to record the video signal thereof in the VTR. In this case, since the video signal which is provided by picking up the negative film is in such a state that the black and white levels of the video signal are inverted relative to the real object, such video signal must be recorded on the VTR under the state that the polarity thereof is inverted by a video signal inverting or nega-posi inverting circuit so to have the normal polarity.
FIG. 1 shows an example of a conventional video signal inverting or nega-posi inverting circuit.
In FIG. 1, a reference numeral 1 designates an input terminal to which a video signal S.sub.V picked up by, for example, a television camera is supplied. Such video signal S.sub.V is supplied to the base of a transistor Q2 which constitute a differential amplifier 2 together with a transistor Q.sub.1 and also to the base of a transistor Q3 which constitute a differential amplifier 3 together with a transistor Q4. These differential amplifiers 2 and 3 are alternately changed over by switching transistors Q5 and Q6 connected differentially relative to a current source 4 depending on the mode whether the input signal S.sub.V is positive, wherein the black and white levels thereof keep a normal polarity relation therebetween and the output signal is derived with the same polarity as that of the input signal (hereinafter, referred to as posi-mode) and the mode when the input video signal S.sub.V is positive, wherein the polarity relation between the black and white levels of the video signal is inverted and the output is derived with the inverted polarity to the input (hereinafter, referred to as nega-mode).
The collectors of the transistors Q2 and Q4 are connected together and the connection point thereof is connected through a resistor 5 to a power source terminal 9. Accordingly, when the differential amplifier 2 is in operation, at the connection point of the collectors of the transistors Q2 and Q4 appears a video signal which is provided by inverting the incoming video signal S.sub.V in polarity, while when the differential amplifier 3 in operation at the above connection point appears a video signal which has the same polarity as that of the incoming video signal S.sub.V. The video signal thus appeared at the connection point of the collectors of the transistors Q2 and Q4 is then supplied to a differential amplifier 7 which is formed of transistors Q7 and Q8 connected differentially to a current source 6. This video signal is obtained with the same polarity at an output terminal 8 led out from a common connection point of the emitters of the transistors Q7 and Q8.
A reference numeral 10 designates an input terminal to which a nega-mode/posi-mode switching signal S.sub.NP is applied. The nega-mode/posi-mode switching signal S.sub.NP is high level in the posi-mode and is low level in the nega-mode.
A reference numeral 11 designates an input terminal to which a horizontal blanking pulse HB is applied. The horizontal blanking pulse HB becomes low in level during a horizontal blanking period T.sub.HB. The horizontal blanking pulse HB is supplied to a base of a transistor Q9 which is connected differentially to a transistor 10. On the other hand, the switching signal S.sub.NP from the input terminal 10 is supplied to a base of the other transistor Q10 and to a base of a transistor Q11. A collector of the transistor Q11 is connected to a base of the transistor Q5.
Consequently, in the posi-mode, the switching signal S.sub.NP becomes high level, therefore the transistors Q10 and Q11 are turned on and hence the collectors thereof become low level in potential. As a result, the transistor Q5 is turned off and the transistor Q6 is turned on so that the differential amplifier 3 becomes operative. Thus, at the output terminal 8 appears an output video signal of the same polarity as that of the incoming video signal S.sub.V.
At this time, let it be considered the case when a video signal having pedestal level E2 as shown in FIG. 2A is supplied to the input terminal 1. If the comparing reference voltage of the differential amplifiers 2 and 3 is taken as E2, the current value of the current source 4 is taken as 2I.sub.4 and the resistance value of the resistor 5 is taken as R.sub.5, the output video signal of the differential amplifier 3 obtained at the collector of the transistor Q4 is a video signal of the same polarity as that of the incoming video signal S.sub.V and the pedestal level of which is expressed as V.sub.CC -I.sub.4 .multidot.R.sub.5 (V.sub.CC is the power source voltage) as shown in FIG. 2B. Accordingly, at the output terminal 8 is obtained the output video signal of the same polarity as that of the incoming video signal S.sub.V and the pedestal level of which is given by (V.sub.CC -I.sub.4 .multidot.R.sub.5 -V.sub.BEQ7) as shown in FIG. 2C.
Although the horizontal blanking pulse HB of the incoming video signal S.sub.V is supplied through the input terminal 11 to the base of the transistor Q9, the transistor Q9 is in the off-state in the posi-mode so that the switching relation is not affected at all. Moreover, in posi-mode, a comparing reference voltage E3 is set in such a manner that the base potential of the transistor Q8 always becomes lower than the base potential of the transistor Q7 in the differential amplifier 7.
In the nega-mode in which the switching signal S.sub.NP becomes at low level, the transistor Q11 is turned off, so that the transistor Q5 turns on and hence the transistor Q6 turns off. Thus, the differential amplifier 2 is operated to apply to the base of the transistor Q7 a video signal which is provided by inverting the incoming video signal S.sub.V in polarity. In nega-mode, the transistor Q9 is turned on so that in response to the horizontal blanking pulse HB supplied to the base thereof, a transistor Q12 connected between a common connection point of the collectors of the differential amplifiers 2 and 3 and the ground is turned off when the pulse HB is at high level, while the transistor Q12 is turned on when the pulse HB is at low level. Therefore, the differential amplifier 2 supplies such output signal on which the pulse of the same polarity as that of the pulse HB is superimposed on the incoming video signal.
More particularly, if the incoming video signal S.sub.V is the signal as shown in FIG. 2A, the video signal supplied to the base of the transistor Q7 of the differential amplifier 7 becomes such a signal as shown in FIG. 3A, wherein the incoming video signal is inverted in polarity with the potential (V.sub.CC -I.sub.4 .multidot.R.sub.5) as the center, and further the pulse of the same polarity as that of the pulse HB is superimposed thereon during the period T.sub.HB and it becomes lower than the reference voltage E3. As is clear from FIG. 3A, in this case, the reference voltage E3 is selected to be the same potential as that of the portion of the original signal corresponding to the 100% white level when the signal is inverted in polarity as described above.
Then, at the output terminal 8 is obtained an output video signal having a pedestal level of E3-V.sub.BEQ7 and the 100% white level of (V.sub.CC -I.sub.4 .multidot.R.sub.5 -V.sub.BEQ7) as shown in FIG. 3B when the above output video signal is regarded as the video signal of the normal polarity.
As described above, the polarity of the video signal is inverted in the nega-mode. As is clear from the above description, in the conventional video signal inverting circuit, the pedestal level of the output video signal is changed in posi-mode and nega-mode. Therefore, in order that the pedestal levels of the video signal in nega-mode and posi-mode may coincide with each other before the video signal is supplied to a video processing circuit which is provided at the output side of the video signal inverting circuit, the conventional video signal inverting circuit requires an additional clamp circuit to make the pedestal levels equal to a predetermined level. Besides, this additional clamp circuit causes a problem of the follow-up property of the clamp operation when the polarity of the input signal is changed in the nega-mode and the posi-mode.